Data processing apparatus having DRAM incorporated therein

ABSTRACT

The present invention may be introduced to an architecture such as a personal computer or an amusement equipment for realizing a high-speed graphic processing and provides an optimum arrangement along the flow of information in the case where a frame buffer, a command memory and an image processor are incorporated in one chip in order to improve the drawing performance of an image processing device. Thereby, unnecessary drawing-around of wiring is eliminated and it is possible to reduce the chip area. Further, since the wiring length is shortened, signal delay becomes small, thereby enabling a high-speed operation.

TECHNICAL FIELD

The present invention relates to a semiconductor integrated circuitdevice, and more particularly to a semiconductor integrated circuitdevice in which a data processing device for performing an imageprocessing and a memory device for storing image data or instructionsare incorporated.

BACKGROUND ART

In recent years, personal computers have pushed into the field of workstations with intent to realize alternate for large-size computers bythe network configuration of work stations. Also, an architecture forrealizing a low-cost and high-speed graphic processing has recently beenneeded with the advance of home amusement equipments. In particular, amodified sprite processing for freely mapping source data of rectanglesforms the basis of a three-dimensional graphics processing and isexpected to have a drawing performance on the order of several tenthousands of polygons per second in order to realize more real display.

In order to improve the drawing performance of graphic LSI, a labor istaken for an improvement in the rate of data transfer between thegraphic LSI and a frame buffer. A method for improving the data transferrate includes (1) a method in which a high-speed interface is used and(2) a method in which a data bus width between the graphic LSI and theframe buffer is enlarged.

In the case of the method (1), the improvement in data transfer rate isrealized using a DRAM provided with a high-speed page mode or asynchronous DRAM. The method using the synchronous DRAM is disclosed byJP-A-7-160249.

In the case of the method (2), the improvement in data transfer rate isrealized by incorporating a frame buffer and a graphics controller inone chip with 128 bits or the like as the bit width of an internal bus.An example having a DRAM and a graphics controller incorporated in onechip is disclosed by “DEVELOPMENT OF GRAPHIC LSI HAVING FRAME BUFFERINCORPORATED THEREIN”, Nikkei Electronics, p. 17 (Apr. 10, 1995) and“ONE-CHIP IMPLEMENTATION WITH LOGIC—DRAM FORMS CORE OF SYSTEM”, NikkeiMicrodevice, pp. 44-65 (March, 1996).

In the frame buffer incorporated graphic LSI disclosed by NikkeiElectronics, a portion of a 16-Mbit general purpose standard DRAMcorresponding to 9 Mbits is removed and thereinstead replaced by a logiccircuit including a controller. Regarding a DRAM incorporated graphiccontroller disclosed by Nikkei Microdevice, this reference has nospecific disclosure excepting that the DRAM is incorporated.

DISCLOSURE OF INVENTION

However, in the case where the general purpose standard DRAM or the likeis modified to incorporate the frame buffer in the graphic LSI as in theabove-mentioned prior art, a restriction is imposed on the arrangementof a graphic controller since the mat construction of the memory, theinput/output direction of data and so forth are determined by thespecification of the general purpose standard DRAM. Also, unnecessarydrawing-around of wiring is caused in order to provide an interface withthe graphic controller.

Namely, in the case where the conventional general purpose standard DRAMor synchronous DRAM is incorporated as it is, it is difficult to obtainthe optimum chip size. Also, since the graphic controller is filled in avacant space of the DRAM, it becomes impossible to use a macro cell ofthe existing graphic controller as it is.

Further, the incorporation of the DRAM results in that a bus for makingan access by the graphic controller to the DRAM does not appear on theexternal side. Accordingly, it becomes impossible to employ theconventional test method. Namely, in the case of the conventionalseparate-chip construction in which a graphic controller and an imagememory such as a frame buffer are provided on separate chips, the directdetection from terminals of the image memory is possible upon physicalfault of the connection terminals of the graphic controller and theimage memories and even upon functional fault thereof. On the otherhand, in the case of a one-chip construction in which a graphiccontroller and a image memory are provided on one chip, it will beimpossible to directly monitor communication of information withterminals of the image memory.

An object of the present invention is to realize the optimum layout of asemiconductor integrated circuit device in which an image memory and animage processor are incorporated.

Another object of the present invention is to allow a semiconductorintegrated circuit device with a logic and a memory incorporated thereinto use the conventional test method for test of the memory as it is.

A further object of the present invention is to realize an incorporatedimage memory having an increased memory address depth and a capacitywhich is large when seen from an image processor.

A furthermore object of the present invention is to facilitate thecontrol logic of a state machine of a logic of a semiconductorintegrated circuit device in which the logic and a memory areincorporated.

The summary of typical ones of inventions disclosed by the presentapplication will be mentioned in the following.

A a semiconductor integrated circuit device having an image memory andan image processor incorporated therein is arranged along the flow ofinformation.

Also, a semiconductor integrated circuit device is provided with a testbus for an incorporated memory to allow the output to the exterior.Further, the incorporated memory is provided with a normal port and atest port.

Also, each of image memories incorporated in a semiconductor integratedcircuit device is constructed by a plurality of identical memory moduleseach of which is allotted with the same row address.

Also, in the case where a logic incorporated in a semiconductorintegrated circuit device makes an access to a memory, the latency of amemory read operation and that of a memory write operation are madeequal to each other.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 shows an example of a system which uses a semiconductorintegrated circuit device according to the present invention.

FIG. 2 shows a typical one of an image operation.

FIG. 3 shows a block diagram of an edge operating section of an imageprocessor incorporated in a semiconductor integrated circuit deviceaccording to the present invention.

FIG. 4 shows a block diagram of a line operating section of the imageprocessor incorporated in the semiconductor integrated circuit deviceaccording to the present invention.

FIG. 5 shows a block diagram of a dot operating section of the imageprocessor incorporated in the semiconductor integrated circuit deviceaccording to the present invention.

FIG. 6 shows a connection relationship between the image processor andan image memory which are incorporated in the semiconductor integratedcircuit device according to the present invention.

FIG. 7 shows a basic timing chart for reading and writing for a memorymodule incorporated in the semiconductor integrated circuit deviceaccording to the present invention.

FIG. 8 shows a timing chart in the case where a change-over between rowaddresses of the memory module incorporated in the semiconductorintegrated circuit device according to the present invention is made.

FIG. 9 shows the case where there is generated a drawing which extendsover a plurality of banks.

FIG. 10 shows a four-stage pipe-line processing by the image processorincorporated in the semiconductor integrated circuit device according tothe present invention.

FIG. 11 shows a specific example of the memory module incorporated inthe semiconductor integrated circuit device according to the presentinvention.

FIG. 12 shows a schematic construction of a layout image of thesemiconductor integrated circuit device according to the presentinvention.

FIG. 13 shows an example of the layout of memory modules incorporated inthe semiconductor integrated circuit device according to the presentinvention.

FIG. 14 shows another example of the layout of memory modulesincorporated in the semiconductor integrated circuit device according tothe present invention.

FIG. 15 shows a test mechanism of the semiconductor integrated circuitdevice according to the present invention.

FIGS. 16a-16 c show a test function for the memory module incorporatedin the semiconductor integrated circuit device according to the presentinvention.

FIG. 17 shows an example of a change-over circuit of the memory moduleincorporated in the semiconductor integrated circuit device according tothe present invention.

FIG. 18 shows the allotment of test control pins of the semiconductorintegrated circuit device according to the present invention.

FIG. 19 shows the input/output of each test terminal of thesemiconductor integrated circuit device according to the presentinvention at the time of logic test.

FIG. 20 shows a block diagram of the whole of the semiconductorintegrated circuit device according to the present invention.

FIGS. 21a, 21 b, 22 a, 22 b, 23 a and 23 b show input/output pins of thesemiconductor integrated circuit device according to the presentinvention.

BEST MODE FOR CARRYING OUT THE INVENTION

The present invention will be explained in accordance with theaccompanying drawings in order to make more detailed description of theinvention.

FIG. 1 shows an example of a system which uses a semiconductorintegrated circuit device according to an embodiment the presentinvention. The system shown in FIG. 1 forms a part of a data processingsystem such as a personal computer or an amusement equipment.

A semiconductor integrated circuit device SIC is composed of an imageprocessor GP, a command/source data image memory (hereinafter referredto as command memory) VRAM and drawing/display memories (hereinafterreferred to as drawing memories) FB0 and FB1. The semiconductorintegrated circuit device SIC is formed on one semiconductor substratesuch as a silicon substrate and is resin-sealed (or sealed in a plasticpackage). The semiconductor integrated circuit device SIC is connectedto a central processing unit CPU and a CRT control circuit DP.

The central processing unit CPU makes an access to the image processorGP through a bus control circuit BC1. In the image processor GP, anoutput from the bus control circuit BC1 divides through the CPUinterface unit CIU into a bus BUS1 which makes an access to the drawingcommand fetch section DCF and a bus BUS2 which makes an access to thecommand memory VRAM.

In the case where an access is made to the drawing command fetch sectionDCF from the CPU interface unit CIU, a command and input data to beprocessed are read from the command memory VRAM and are then supplied tothe drawing controller DM, performing image data operation, such as theedge operating section EDGE, the line operating section LINE, the dotoperating section DOT and so forth.

More particularly, the drawing command fetch section DCF issues anexecution start command to fetch a command from the command memory VRAM,transfers necessary parameters to the edge operating section EDGE, theline operating section LINE and the dot operating section DOT, andactivates the edge operating section EDGE. The edge operating sectionEDGE calculates an input data storing coordinate (or a coordinate atwhich the input data is stored) and a drawing coordinate in units of oneend point and activates the line operating section LINE. The lineoperating section LINE operates an input data storing coordinate and adrawing coordinate in units of one dot and instructs the dot operatingsection DOT to perform the processing of data. The dot operating sectionDOT takes the input data out of the command memory VRAM to process thedata. After the processing of the data, the dot operating section DOTperforms the drawing into either the drawing memory FB0 or the drawingmemory FB1 through the bus controller BC3 and the change-over switch SW.Which one of the drawing memories FB0 and FB1 is the drawing startedfrom, is determined in accordance with a state after resetting.

One of the drawing memories FB0 and FB1 being not subjected to drawingis subjected to a read processing by the display controller DISP throughthe bus controller BC4 and the change-over switch SW. The displaycontroller DP transfers the read data to the display processor DPthrough a display output bus BUS3. The display processor DP converts thedisplay data into a video signal and sends the video signal to a displaydevice CRT.

The case where the command memory VRAM is accessed from the CPUinterface unit CIU includes the case of the testing of the imageprocessor GP. In this case, an external data processing device such as alogic tester stores a test command into the command memory VRAM throughthe CPU interface unit CIU. The testing of the image processor GP isperformed in such a manner that the image processor GP executes thestored test command on the basis of an instruction from the externaldata processing device.

The command memory VRAM is constructed by a 4-M(M=1048576)bit dynamicRAM (Random Access Memory hereinafter referred to as DRAM). Each of theimage memories FB0 and FB1 is constructed by a 2-Mbit DRAM.

Before the detailed explanation of the image processor GP, descriptionwill be made of an image processing. In order to realize an imageprocessing which copes with three dimensions, an image pattern called atexture mapping is put on the surface of an object. This requires afunction of mapping a rectangular source pattern to a destinationpattern shown by four arbitrary points. This function is called amodified sprite processing. With the incorporation of a predeterminednumber of small-area image patterns in an image processing device, thepatterns are moved on a background image at a high speed. By performingthis modified sprite processing, a perspective representation becomespossible so that more real display can be realized.

In mapping the rectangular source pattern to the destination patternshown by four arbitrary points, it is necessary to perform an imageoperation including the enlargement, reduction and rotation of theoriginal picture image. A typical one of the image operation is shown inFIG. 2. FIG. 2(a) represents a function of mapping a rectangular sourceimage ABCD to an arbitrary rectangle A′B′C′D′.

The image processor GP uses a system in which this mapping is realizedby performing line copy plural times. The line copy corresponds to animage operation in which a row of horizontal dots P0(Xp0, Yp0) toP1(Xp1, Yp1) of the source image are mapped to an arbitrary line fromQ0(Xq0, Yq0) to Q1(Xq1, Yq1) on a destination space, as shown in FIG.2(b). The image processor GP performs an edge operation of determiningthe start and end points Q0 and Q1 of the line copy and a line operationof determining a line which connects the start point Q0 and the endpoint Q1. The image processor GP can perform the modified spriteprocessing at the highest 29 Mdots/sec in accordance with a macrocommand from the external data processing device.

FIG. 3 shows a detailed block diagram of the edge operating sectionEDGE. The edge operating section EDGE is composed of two 13-bitarithmetic units AUa and AUb each having dedicated read and write buses,13-bit registers (R1-Rn) common to the two arithmetic units AUa and AUb,13-bit registers (Ra1-Ran, Rb1-Rbn) for the exclusive use of the twoarithmetic units AUa and AUb, an address decoder 121 for selecting theregisters (R1-Rn, Ra1-Ran, Rb1-Rbn), and an edge operating sectionsequencer 122 for controlling the arithmetic units AUa and AUb and soforth.

The edge operating section EDGE is a module which executes an edgedrawing algorithm. Also, the edge operating section EDGE fetches adrawing command, drawing source data and drawing parameters from thecommand memory VRAM. The fetched command and parameters are stored intointernal registers provided in the edge operating section EDGE and thedot operating section DOT. The edge operating section EDGE performs anedge operation in accordance with the fetched drawing command anddrawing parameters and stores the result of edge operation an internalregister provided in the line operating section LINE.

FIG. 4 shows a detailed block diagram of the line operating sectionLINE. The line operating section LINE is composed of five DDA (DigitalDifferential Analyzer) arithmetic units (S-DDA, D-DDA, R-DDA, G-DDA,B-DDA) for performing a DDA operation (an operation of mainly performingsubtraction) in one cycle, a 13-bit register group 132, an addressdecoder 131 for selecting the register group 132, and so forth.

The line operating section LINE is a module which executes a linedrawing algorithm. The line operating section LINE performs a lineoperation in accordance with the result of edge operation stored by theedge operating section EDGE. Parameters of the start and end points of aline copy received from the edge operating section EDGE are stored inthe register group 132 incorporated in the line operating section LINE.The line operating section LINE performs the line operation on the basisof the stored parameters.

FIG. 5 shows a detailed block diagram of the dot operating section DOT.The dot operating section DOT is composed of a source memory addresscounter S-Counter, a destination memory address counter D-Counter, three5-bit counters R-Counter, G-Counter and B-Counter corresponding to red,green and blue, three 5-bit arithmetic units R-AU, G-AU and B-AU eachhaving dedicated read and write buses, and so forth.

Each of the source memory address counter S-Counter and the destinationmemory address counter D-Counter makes the count-up of address when acarry is generated as the result of operation. Each of the three 5-bitcounters R-Counter, G-Counter and B-Counter makes the count-up of colordata when a carry is generated as the result of operation. Each of thethree 5-bit arithmetic units R-AU, G-AU and B-AU makes the addition ofsource data red, green or blue and red, green or blue generated by the5-bit counter R-Counter, G-Counter or B-Counter.

The dot operating section DOT is a module which executes a dot copyalgorithm. The dot operating section DOT performs an address operationand a dot operation of data for the drawing memory in accordance withthe result of line operation. The dot operating section DOT performs anaccess to the command memory VRAM for reading of source data, the dotoperation and an access to the drawing memory FB0 or FB1 for writing ofthe result of dot operation. The dot operation is an operation ofdetermining a source coordinate P of a certain dot on a line copy, adestination coordinate Q thereof and color data (R, G, B) of thedestination coordinate Q and is determined by an increment from aninitial value.

The display controller DISP reads display data from the drawing memoryFB0 or FB1 and sends the read display data to the display processor DP.In the display controller DISP is incorporated a refresh circuit forrefreshing the command memory VRAM and the drawing memories FB0 and FB1.The refresh circuit refreshes the command memory VRAM and the drawingmemories FB0 and FB1 simultaneously. The refresh cycle is performed inreference to the command memory VRAM.

Usually, in the case where a DRAM is externally mounted to the imageprocessor, the refresh circuit includes a register for refresh cycle inorder to cope with various DRAM's. The CPU performs the writing into therefresh cycle register in compliance with the specification of a DRAM orthe like, thereby determining a refresh cycle.

In the present embodiment, however, since the image processor GP, thecommand memory VRAM and the drawing memories FB0 and FB1 are formed onone semiconductor integrated circuit device, the number of refreshcycles and the number of clocks for the command memory VRAM and thedrawing memories FB0 and FB1 are known beforehand and can be fixed.

With this construction, clocks conformable to the command memory VRAMare inputted from the display controller DISP to the command memory VRAMand the drawing memory FB0 or FB1, thereby unifying the refresh cycle ofthe image processing device having a plurality of DRAM's mountedthereon. Also, the display controller DISP can know a flyback period ofthe display device CRT and therefore performs the refreshing of the DRAMby use of the flyback period.

In the present embodiment, the command memory VRAM uses a 4-Mbit DRAM.Therefore, the drawing memories FB0 and FB1 using 2-Mbit DRAM's arerefreshed two times.

FIG. 6 shows a connection relationship of the image processor GP withthe command memory VRAM and the drawing memories FB0 and FB1.

The 4-Mbit DRAM of the command memory VRAM is formed using two 2-MbitDRAM modules of 8-bank construction. Also, each of the 2-Mbit DRAM's ofthe drawing memories FB0 and FB1 is formed using two 1-Mbit DRAM modulesof 4-bank construction. Hereinafter, the DRAM module will also bereferred to as memory module.

Each bank of the command memory VRAM and the drawing memories FB0 andFB1 forms a memory array which has 256 word lines and 1024 bit linepairs. A column selecting circuit selects 128 bit line pairs (8 rowaddresses AX and 3 column addresses AYi). Namely, the bank has a storagecapacity of 256 Kbits (K=1024). With the use of this construction, amemory module can be constructed in units of 256 Kbits by increasing anddecreasing the number of banks. This memory module is suitable for asemiconductor integrated circuit on which logics and memories aremounted together or in a mixed form, as in the present embodiment.

The selection of a bank in the memory module is made by a row address Ri(i=number of banks) and a column address Ci. Also, a byte enable signalBE enables the input/output of 128-bit data at every n times (n=1 16) aslarge as 8 bits (or 1 byte).

The memory module is a so-called synchronous type DRAM in which anaddress signal and a control signal are inputted in synchronism with aclock signal and data is also inputted in synchronism with the clocksignal. Accordingly, the memory module operates in accordance with aso-called command designated by the control signal and the addresssignal. Also, a row address and a column address are notmultiplex-inputted as in a general purpose standard DRAM.

Between the image processor GP and the command memory VRAM are connecteda 16-bit data bus DBUS16, a 11-bit address bus (A0-A10), and signalswhich include 8-bit row bank address (R0-R7), 8-bit column bank address(C0-C7), row address control CR, column address control CC0, CC1, 16-bitbyte enable BE, read/write RW, active control AC, clock CK and so forth.

Between the image processor GP and the drawing memories FB0 and FB1 areconnected a 32-bit data bus DBUS32, a 11-bit address bus (A0-A10), andsignals which include 4-bit bank address (R0-R3), row address controlCR, column address control CC0, CC1, 16-bit byte enable BE, read/writeRW, active control AC, clock CK and so forth.

FIG. 7 shows the basic timing for reading and writing for the memorymodule. Namely, there is represented the basic timing which concerns aseries of operations including the reading of source data from thecommand memory VRAM, the image conversion of the source data by theimage processor GP and the writing of the image converted data into thedrawing memory FB0 or FB1.

An address ADDRVRAM of the command memory VRAM and an address ADDRFB ofthe drawing memory FB0 or FB1 are generated by the image processor GPand are then inputted to the command memory VRAM and the drawing memoryFB0 or FB1, respectively. Also, a control signal necessary for thememory modules is generated by the image processor GP and is theninputted to the command memory VRAM and the drawing memory FB0 or FB1.An active control AC, a row address control CR and a row address AX aretaken into the memory module upon falling of a clock signal CK toactivate a bank (T0). After two clocks, an address control CC,read/write RW and a column address AYi are taken into the memory moduleupon falling of the clock signal CK (T2). After further two clocks, datais read (T4).

Namely, source data (READ1) is read after four clocks subsequent to thetaking of the row address AX into the command memory VRAM. Similarly,dot data (READ2) is read after four clocks subsequent to the taking ofthe row address into the drawing memory FB.

In the image processor GP, the source data (READ1) read from the commandmemory VRAM and the dot data (READ2) read from the drawing memory FB arelatched by the bus controller BC2 (SET0) and synthetic data (SET1) isgenerated by the dot operating section DOT.

Further, the image processor GP outputs an address and a control signalin order to write the synthetic data (SET1) into the drawing memory FB0or FB1. Address control CC, read/write RW and column address AYi aretaken into the memory module upon falling of the clock signal CK (T7).After two clocks, the writing of data (WRITE1) is performed (T9).Thereby, the synthetic data (SET1) is written into the drawing memoryFB.

In the present embodiment, the latency of reading from the memory module(or a time from the input of a read command until data can be read) istwo clocks and the latency of writing into the memory module (or a timefrom the input of a write command until data is written) is one clock.Therefore, in the case of writing, the image processor GP inserts NOPfor one cycle to match the write cycle and the read cycle with eachother. Thereby, it is possible to treat a read processing and a writeprocessing in the state machine without discrimination and it becomesunnecessary to consider the access combinations of read/write,write/read, read/read and rite/write in the state machine. Thereby, itis also possible to reduce the number of logic gates of the imageprocessor.

In the case where a change-over between row addresses AX is made, it isnecessary to reserve two locks for a pre-charging time from the supplyof a row address AX until the issuance of a column address AY0, as shownin FIG. 8(a). Namely, the column address AY0 is issued after threeclocks subsequent to the supply of the row address AX0. In the casewhere data in the same row address AX0 is to be accessed subsequently,it is possible to issue column addresses AY1 and AY2 continuously. Inthe case where three dots extending over a plurality of banks are to bedrawn, as shown in FIG. 9, it is necessary to reserve two clocks as apre-charging time from the supply of the row address AX0 until theissuance of a column address AY3, it is necessary to reserve two clocksas a pre-charging time from the supply of a row address AX2 until theissuance of a column address AY4. Namely, it is not possible to continuethe issuance of column addresses and eleven clocks are required untilthe issuance of the third column address AY5, as shown in FIG. 8(b).

Thus, it is possible to continue the issuance of column addresses AYapparently by issuing a row address AX three clocks before a change-overbetween row addresses AX is made. In the present embodiment, this isrealized by a 4-stage pipe-line processing as shown in FIG. 10.

First, for a bank B0, a change-over between row addresses AX is detectedat a first stage (B0:X-Y) so that a row address (B0:AX0) is issued (T0).In a second stage and a third stage, NOP is performed to ensure apre-charging time (T1, T2). At a fourth stage, a column address (B0:AY3)is issued (T3).

Next, for a bank B2, a change-over between row addresses AX is detectedat the first stage (B2:X-Y) so that a row address (B2:AX1) is issued(T1). In the second stage and the third stage, NOP is performed toensure a pre-charging time (T2, T3). At the fourth stage, a columnaddress (B2:AY4) is issued (T4).

Next, for a bank B3, a change-over between row addresses AX is detectedat the first stage (B3:X-Y) so that a row address (B3:AX1) is issued(T2). In the second stage and the third stage, NOP is performed toensure a pre-charging time (T3, T4). At the fourth stage, a columnaddress (B3:AY5) is issued (T5).

By thus performing the 4-stage pipe-line processing, the columnaddresses of the three banks can be issued continuously. Thereby, in ausual state of use, the performance is improved corresponding to theabsence of a wait caused by a mishit cycle.

The detection of change-over between row addresses AX can be realized bycomparing a row address AX of the preceding cycle and a row address AXof the present cycle by a comparator in the bus controller BC2, BC3 orBC4.

The reason why two memory modules are used for each of the commandmemory VRAM and the image memories FB0 and FB1, is that the same rowaddress AX is inputted to the two memory modules simultaneously todouble the number of bits accessed by the same row address AX. Thisreason will be explained in the following.

In the memory module of the present embodiment, the number of bitscapable of being made active by the row address issuance performed onceis 1024 bits. In the case where data existing at the same row address AXis to be accessed (hitting), a read command or write command can beissued immediately. However, in the case where an access is to be madeto data which do not exist at the same row address AX (mishitting), theread command or write command cannot be issued immediately in order toensure a pre-charging time.

If the same row address is allotted to the two memory modules and therow address is inputted to those modules simultaneously, the row addressaccess performed once enables the activation of 2048 bits which are twotimes as compared with the case where the row address is inputted to onemodule. In this case, column address control CC uses one characteristicof each memory module. In the present embodiment, two column addresscontrols CC0 and CC1 are used to select columns.

In the case of mishitting, the image processor GP takes three clockcycles to make two banks of the two memory modules active. Namely, aplurality of banks are made active simultaneously, thereby reducingoverhead at the time of bank change-over.

In the case where four memory modules are used for each of the commandmemory VRAM and the image memories FB0 and FB1, the command memory usesa 1M memory module and each of the image memories FB0 and FB1 uses a512K memory module. In this case, the row address access performed onceenables the activation of 4096 bits which are four times as comparedwith the case where the row address is inputted to one module.

If a row address AX is being hit in the memory module of the presentembodiment, a read or write processing can be performed continuously byoutputting only column addresses AY. However, when the row address AX ismishit, a row address is issued after pre-charging. Therefore, it isnecessary to take a wait of several cycles for the issuance of acommand. Accordingly, if a mishitting is generated at the time ofwriting of destination data during a period of time when source data isbeing read without mishitting, there results in the overflow andextinction of data. In the present embodiment, therefore, the mishittingat the time of writing is detected in advance to wait for data bycausing a mishitting operation even if the reading on the source dataside is not mishit. Inversely, if the reading on the source data side ismishit, the mishitting operation is also performed at the time ofwriting on the destination side.

FIG. 11 shows a specific construction of the memory module in thepresent embodiment. The memory module is composed of three kinds ofmodules including a bank module BANK, an amplifier module AMP and apower supply module PS. FIG. 11 shows the memory module in a formresembling to the actual layout.

The bank module BANK includes BANK-0 to BANK-n and is composed of aplurality of submemory arrays SUBARY (BUBARY-00 to SUBARY-i7), a bankcontrol circuit BNKCNT-1 and a bank control circuit BNKCNT-2.

The submemory array SUBARY includes a plurality of pairs of bit lines Band /B, a plurality of word lines W, a plurality of memory cells(represented by circular symbol in the figure), a bit line pre-chargingcircuit PC for bringing the potential of the bit line into apredetermined level before reading from the memory cell, a senseamplifier SA for amplifying a signal from the memory cell, a Y selectingcircuit for selecting one of the plurality of pairs of bit lines B and/B, and global bit lines GBL and /GBL for connecting the selected bitlines B and /B to an amplifier module AMP. The submemory array SUBARY isa divisional unit of I/O line in the bank module BANK.

The bank control circuit BNKCNT-1 includes an X decoder XD for selectingthe word line W, a Y decoder YD for selecting the bit lines B and /B,and so forth. Receiving a bank address and a control signal which willbe mentioned later on, the bank control circuit BNKCNT-1 automaticallygenerates signals necessary for a series of memory cell read operationsincluding the pre-charging of bit line, the selection of word line, theactivation of sense amplifier, and so forth. One word line W is selectedby the X decoder XD, and (8×i) pairs of (n×8×i) pairs of bit lines B and/B (n=8 in the present embodiment though the case of n=2 is shown inFIG. 11 for restriction by the size of drawing) intersecting theselected word line W are selected by an output signal YSi of the Ydecoder YD. The selected bit lines B and /B makes the delivery andreception of data to and from the amplifier module AMP through theglobal bit lines GBL and /GBL arranged parallel to the bit lines B and/B.

The bank control circuit BNKCNT-2 includes a group of sensors fordetecting the reaching of a sense amplifier control signal to a certainlevel.

The amplifier module AMP is composed of a main control circuit MAINCNTfor supplying a control signal, an address signal and so forth to thebank module BANK in synchronism with a clock signal, and a byte controlcircuit BYTCNT for controlling the reading and writing of data for thegroup of bank modules (BANK-0 to BANK-n). Through the amplifier moduleAMP, (8×i) data input/output lines DQ (DQ00, - - - , DQ07, - - - ,DQ07, - - - , DQi7) from the exterior of the memory module are inputtedto the memory cells. A byte control signal BEi is a signal for turningthe data input/output lines DQ on and off in units of one byte.

The power supply module PS is a module for generating various voltagesand includes a VCH generating circuit VCHG for generating a word linevoltage VCH (higher than a power supply voltage VCC) supplied to thebank module BANK and necessary for a word line driving circuit WD, a bitline pre-charge voltage generating circuit HVCG for generating a voltageHVC (equal to one half of the power supply voltage VCC) necessary forpre-charging the bit lines, an in-array substrate voltage generatingcircuit VBBG for generating an in-array substrate voltage (or a backbias voltage) VBB (lower than a power supply voltage VSS (or groundpotential)), and so forth.

The bank module BANK of the present embodiment includes 256 word lines.One word line intersects (8×8×i) pairs of bit lines the one-eighth ofwhich is selected to the Y decoder so that (8×i) pairs of global linesare inputted and outputted. In the present embodiment, i is 16 so thatone bank module BANK has a capacity of 256 Kbits and is inputted andoutputted with data with a 128 bit width. Namely, there is obtained amemory macro module the capacity of which is variable with the size of256 Kbit unit. The bank module BANK-n corresponds to one of theplurality of banks B0 to B7 shown in FIG. 6.

The schematic construction of the layout image of the semiconductorintegrated circuit SIC according to the present invention is shown inFIG. 12. The semiconductor integrated circuit SIC has a laterallyelongated form which has the command memory VRAM arranged on the leftside thereof and the drawing memories FB0 and FB1 arranged on the rightside thereof. The image processor GP is arranged between the left andright sides.

An example of the layout of memory modules is shown in FIG. 13. Thecommand memory VRAM has two mirror-symmetrically arranged 2-Mbit memorymodules so that an address bus, a data bus, a control signal and soforth are inputted and outputted from a space between the two memorymodules. Each of the drawing memories FB0 and FB1 has twomirror-symmetrically arranged 1-Mbit memory modules so that an addressbus, a data bus, a control signal and so forth are inputted andoutputted from a space between the two memory modules.

In the present embodiment, a bus width between the image processor GPand the memory module is 16 bits or 32 bits or relatively small. Sincethe memory module has a 128-bit width at the largest, it is possible toenlarge the bus width between the image processor GP and the memorymodule to 128 bits. In that case, the change of arrangement of memorymodules as shown in FIG. 14 facilitates the provision of a datainput/output interface.

The command memory VRAM and the drawing memories FB0 and FB1 have thesame storage capacity and are different in the manner of construction ofmemory modules but the power supply module and the amplifier module aresmall as compared with the bank module. Accordingly, the command memoryVRAM and the drawing memories FB0 and FB1 can be provided substantiallywith the same form and the same area. Namely, though the command memoryVRAM and the drawing memories FB0 and FB1 are shown in FIG. 13 to havedifferent sizes, an actual difference in size therebetween is not solarge.

According to the present embodiment, the exchange of information is madealong a flow from the command memory VRAM to the drawing command fetchsection DCF, the edge operating section EDGE, the line operating sectionLINE, the dot operating section DOT, the drawing memories FB0 and FB1,the display controller DISP, the drawing memories FB0 and FB1, and thedisplay controller DISP. Namely, information flows from the left of FIG.12 to the right thereof. Therefore, the drawing-around of wiring becomessimple and the length of wiring becomes short. Also, the wiring area isreduced, thereby reducing the chip area. Further, since the wiringlength becomes short, signal delay becomes small, thereby enabling ahigh-speed operation.

FIG. 15 shows a block diagram of the interior of the semiconductorintegrated circuit device SIC of the present invention concerning a testmechanism.

The semiconductor integrated circuit device SIC is provided with anormal bus NB connected to the image processor GP and used at the timeof normal operation, a normal terminal NT connected to the normal busNB, a common test bus TB connected to the image processor GP, thecommand memory VRAM and the drawing memories FB0 and FB1 and used at thetime of test operation, a test terminal TT connected to the common testbus TB, and a mode selecting terminal MST for controlling modesincluding a normal mode, a test mode and so forth. Module selectingsignals TEM0˜5 are signals outputted from the mode selecting terminalMST for selecting memory modules to be tested. Also, internal buses IB0,IB1 and IB2 are internal buses which are not connected to the exteriorand are used at the time of normal operation.

In the present embodiment, the test of the memory modules of the commandmemory VRAM and the drawing memories FB0 and FB1 and the test of thedrawing processor GP are performed in independent forms. The test of thememory modules is conducted by a memory tester, and the test of thedrawing processor GP is conducted by a logic tester.

Also, the memory module in the present embodiment is provided with anormal port NP used at the time of normal operation and a test port TPused at the time of test operation. This construction is used forlightening the load of the port to the minimum at the time of normaloperation since control logics such as a memory control are connected tothe normal port NP side through the internal buses IB0, IB1 and IB2.However, it is not necessarily required that the normal port and thetest port should be provided separately. The normal port and the testport can be constructed with one port by employing a construction suchas multiplex.

The test of each module is performed by selecting the image processor GPand the memory modules of the command memory VRAM and the drawingmemories FB0 and FB1 are respectively selected by module selectingsignals TEM0˜5 and a mode selecting signal TL which are internal controlsignals outputted from the mode selecting terminal MST. Input signalsTE0˜3 of the mode selecting terminal MST are supplied from an externaltest device (or tester) or an external CPU. Accordingly, the inputsignals TE0˜3 from the exterior generate the module selecting signalsTEM0˜5 and the mode selecting signal TL internally through the modeselecting terminal MST and the generated signals are inputted to therespective modules so that the testing is conducted for each module.

Also, each memory module and the common test bus TB are connected in awired OR manner so that only the output of a memory module selected bythe module selecting signal TEM0˜5 is outputted to the common test busTB.

Thereby, the number of wirings for testing can be reduced and the chiparea of the semiconductor integrated circuit device SIC can be reduced.

A specific construction of the normal port NT and the test port TPprovided in the memory module of the command memory VRAM and the drawingmemories FB0 and FB1 is shown in FIG. 16. The normal port NT and thetest port TP are constructed so that they perform operations which aredifferent for a normal operation mode and test modes, respectively.

FIG. 16a shows the case of the normal operation mode in which thesemiconductor integrated circuit device SIC is performing a normaloperation. In the normal operation mode, the memory module is accessedfrom the normal port NP by the image processor GP. At this time, thetest port TP side is brought into a high-impedance condition on thebasis of a selecting signal so that no information is outputted to theexterior. Namely, at the time of normal operation mode, the operation isperformed in a state in which the image processor GP and the memorymodule are directly coupled to each other. The selecting signal isgenerated by an AND logic of the module selecting signal TEM0˜5 and theinternal control signal TL.

FIG. 16b shows the case of a memory test mode. In the memory test mode,the memory module is accessed from the test port TP. At this time, thenormal port NP side is brought into a high-impedance condition on thebasis of a selecting signal so that no information is outputted to theexterior. Namely, at the time of memory test mode, the operation isperformed in a state in which the image processor GP and the memorymodule are disconnected and the memory module is directly coupled to theexternal test device or the external CPU through the test port TP.

Thereby, the conventional test method for semiconductor memories such asgeneral purpose DRAM's can be used for the memory modules mounted on thesemiconductor integrated circuit device SIC as it is.

FIG. 16c shows the case of a logic test mode. The logic test mode meansa test mode for the image processor GP. In the logic test mode, thememory module is accessed from the normal port NP. Also, the externalmonitoring through the test port TP is possible.

Namely, at the time of logic test mode, the operation is performed in astate in which the image processor GP and the memory module are directlycoupled to each other and the memory module is directly coupled to theexternal test device or the external CPU through the test port TP.Thereby. at the time of logic test mode, the image processor GPcommunicates with the memory module in accordance with a test pattern ofthe logic tester whereas the condition of the memory module at that timecan be monitored.

FIG. 17 shows an example of a circuit for change-over between the normalport NP and the test port TP. The change-over circuit includes atransfer gate TG1 which is composed of an n-channel MOS (nMOS)transistor Q1 and a p-channel MOS (pMOS) transistor Q2 and a transfergate TG2 which is composed of an nMOS transistor Q3 and a pMOStransistor Q4. The transfer gates TG1 and TG2 are controlled by controlsignals SN and ST generated from the mode selecting signal TL and themodule selecting signals TEM0 to TEM5. A similar function can berealized using a clock inverter or the like in place of the transfergate.

FIG. 18 shows the allotment of test control pins of the mode selectingterminal MST. The test control pins (TE0 to TE3) receive a 4-bit encodedsignal so that the internal control signals TEM0˜5 and the modeselecting signal TL are generated on the basis of the 4-bit encodedsignal, as shown in FIG. 18.

The memory modules of the command memory VRAM and the drawing memoriesFB0 and FB1 are selected and tested on the basis of the module selectingsignals TEM0˜5 and the mode selecting signal TL.

The internal control signals TEM are the result of decoding of anexternal input signal supplied to the test control pins (TE0 to TE3) andare inputted to the respective modules of the image processor GP, thecommand memory VRAM and the drawing memories FB0 and FB1 to determine amodule to be tested. In the present embodiment, the signals will be“000000” at the time of normal mode operation and at the time of STNBYmode.

The mode selecting signal TL sets each of modes including a normaloperation mode, a logic test mode and a memory test mode. In FIG. 18,the normal operation mode and the logic test mode are set when the modeselecting signal TL is “1”. The memory test mode is set when the modeselecting signal TL is “0”. In the present embodiment, a stand-by modecan also be set in addition to the normal operation mode, the logic testmode and the memory test mode.

The test module in the present embodiment is such that the test isperformed in units of two memory modules (M0-M1, M2-M3, M4-M5) and thetest in the memory test mode is performed in units of one memory module(M0, M1, M2, M3, M4, M5). This is based on a difference in test methodbetween the logic test mode and the memory test mode. At the time oflogic test mode, the testing is conducted in units of one function suchas the drawing memory FB0 or the drawing memory FB1. At the time ofmemory test mode, on the other hand, the testing is conducted in unitsof one memory module.

With the above construction, there is no need to increase the number oftest control pins (TE0 to TE3) even if the number of mounted memorymodules or banks is increased. Also, it becomes possible to test amodule(s) corresponding to each test method.

It is not necessarily required that the test control pins (TE0 to TE3)should be encoded as in the present embodiment. There may be employed aconstruction in which each test control pin selects a specified memorymodule directly. For example, there may be constructed such that if TE2turns into “1”, one memory module of the drawing memory FB0 is selectedand tested.

FIG. 19 shows the input/output of each terminal at the time of logictest mode shown in FIG. 16(a).

In the present embodiment, therefore, a state directly coupled to theexternal test device or the external CPU is established through the testport NP shown in FIG. 16 and the testing can be conducted for the imageprocessor GP and each memory module accessed by the image processor GP,as shown in FIG. 19.

The testing of the image processor GP in the present embodiment isconducted in a manner that the image processor GP executes a command anda test pattern for testing inputted from the exterior from the normalterminal NT. Accordingly, the image processor GP can use the normalterminal NT to perform a normal operation on the basis of the testpattern. This is not different from the operation at the time of normaloperation.

More particularly, the testing of the image processor GP is conducted insuch a manner that an external data processing device stores the commandand the test pattern for testing into the command memory VRAM throughthe above-mentioned CPU interface unit CIU and the image processor GPexecutes that command on the basis of an instruction from the externaldata processing device.

In the present embodiment, the image processor GP executes the testpattern for each memory module to be tested. Accordingly, the drawingmemory FB0 is first made the object of logic test mode and the drawingmemory FB1 and the command memory VRAM are subsequently made the objectsof logic test mode. Which one of the memory modules should be observedin the logic test mode is determined by the observation change-oversignals KS which are the result of decoding of external input signalsinputted to the test control pins (TE0˜TE3). In the present embodiment,there are a mode 1 in which the drawing memory FB0 is observed, a mode 2in which the drawing memory FB1 is observed and a mode 3 in which thecommand memory VRAM is observed.

With this construction, a state in which the drawing memory FB0 is beingaccessed from the normal port NP, a state in which the drawing memoryFB1 is being accessed and a state in which the command memory VRAM isbeing accessed, can be monitored at the time of mode 1, at the time ofmode 2 and at the time of mode 3, respectively, from the exteriorthrough the test port TP shown in FIG. 16c.

FIG. 20 shows a block diagram of the whole of the semiconductorintegrated circuit device SIC with a view to test, and FIGS. 21 to 23show a summarized form of the contents of input/output pins of thesemiconductor integrated circuit device SIC.

Each memory module is connected to the common test bus TB. The commontest bus TB is composed of a 11-bit address bus A, a 8-bit columnaddress bus C, a 8-bit row address bus R, a 16-bit memory byte enablesignal BE, a 16-bit data bus DQ, clock CLK, active control AC, rowaddress control CR, column address control CC, read/write RW, and soforth.

The semiconductor integrated circuit device SIC has 100 input, outputand input/output terminals in total, that is, 34 input, output andinput/output terminals necessary for the image processor GP at the timeof normal operation, 7 terminals for test control, 43 terminals for theexclusive use for testing, and 16 power supply/ground terminals. Asshown in FIG. 12, twenty five terminals are arranged for each side.

Each of an address/data bus VBUS, a memory byte enable TEBE and a memorybank address TERC is multiplexed in order to reduce the number of pins.For example, the address/data bus VBUS performs as an address/data busthe reading/writing for the image processor GP from the external dataprocessing device at the time of normal operation on one hand and isconnected to the data bus DQ of the test bus TB at the time of memorytest mode on the other hand to effect the input/output of the contentsof the data bus DQ of the test bus TB.

Effects obtained by the present embodiment can be explained briefly asfollows.

(1) According to the present embodiment, the optimum arrangement alongthe flow of information is provided in the case where a frame buffer, acommand memory and an image processor are incorporated in one chip.Thereby, the drawing-around of wiring is simplified and the wiringlength can be shortened. As a result, the wiring area is reduced,thereby making it possible to reduce the chip area. Further, since thewiring length is shortened, signal delay becomes small, thereby enablinga high-speed operation.

(2) With a construction in which an image processing device having aframe buffer, a command memory and an image processor incorporated inone chip is provided with a test terminal and each memory module isprovided with a test port connected to a test bus, it is possible tomonitor the content of each incorporated memory module from the exteriorat the time of test. Accordingly, even if external terminals formemories are removed due to mixed mounting, the conventional test methodcan be used as it is.

(3) With a construction in which each of the frame buffer and thecommand memory incorporated in the image processing device is formed bya plurality of memory modules having the same construction and the samerow address is allotted to each memory module, it is possible toincrease the memory address depth. Thereby, even in the case where thecurrent line or current capacity of the memory module is limited due tophysical restrictions such as stress, torsion and so forth, a framebuffer and a command memory each having a large capacity when seen fromthe image processor can be realized by the plural and same constructionin a range in which the upper limit is satisfied. Further, theconstruction of the frame buffer and the command memory by memorymodules having the same construction enables the unification of testingand/or refreshing in each of the frame buffer and the command memory.

(4) With a construction in which the latencies of reading and writingoperations for each of the frame buffer and the command memory based onan instruction from the image processor are made equal to each other, itis possible to facilitate the control logic of a state machine of alogic. Namely, the image processor makes the latencies of reading andwriting operations equal to each other by executing a non-operationinstruction after the output of a write address. Thereby, it is possibleto handle a read processing and a write processing withoutdiscrimination in the state machine. Accordingly, there is no need toconsider the access combinations of read/write, write/read, read/readand write/write in the state machine. Also, it is possible to reduce thenumber of logic gates of the image processor.

INDUSTRIAL APPLICABILITY

The present invention can be introduced to an architecture such as apersonal computer or an amusement equipment for realizing a high-speedgraphic processing. With a construction in which the optimum arrangementalong the flow of information is provided in the case where a framebuffer, a command memory and an image processor are incorporated in onechip in order to improve the drawing performance of an image processingdevice or with a construction in which the conventional memory test andlogic test can be used as they are and each of a frame buffer and acommand memory is formed by a plurality of memory modules having thesame construction, the present invention is suitable for the reductionof an occupied area on a substrate or the realization of an imageprocessing device in which convenient use is possible.

What is claimed is:
 1. A semiconductor integrated device comprising onone semiconductor substrate an image processor in which logic circuitsare integrated, a first dynamic RAM in which command and source data arestored and a second dynamic RAM in which drawing information is stored,wherein said first dynamic RAM and said second dynamic RAM are arrangedat opposite ends of said image processor, wherein said image processorincludes: a drawing command fetch section for fetching a command fromsaid first dynamic RAM and outputting an edge operation start signalafter completion of fetching; an edge operating section for performingan operation of coordinates of a start point and an end point afterconversion when an original picture to be converted is divided intopredetermined lines; a line operating section for performing anoperation of filling up a space between said start and end points of theline into a straight line and addressing it; a dot operating section fortaking in dot data from said dynamic RAM and starting a memory access tosaid second dynamic RAM to write a drawing address and the dot datatherein; and a display controller for outputting display data of saidsecond dynamic RAM to the exterior.
 2. A semiconductor integrated deviceaccording to claim 1, wherein said drawing command fetch section fetchesa command from said first dynamic RAM by a drawing start signal inputtedfrom an external data processing device and outputs an edge operationstart signal to said edge operating section after completion offetching, said edge operating section receives said edge operation startsignal to start an edge operation and outputs a line operation startsignal to said line operating section after completion of the edgeoperation while setting the result of the edge operation to said lineoperating section and starting a next edge operation, said lineoperating section receives said line operation start signal to start aline operation and outputs a memory access start signal to said dotoperating section after completion of the line operation while settingthe result of the line operation to said dot operating section, said dotoperating section receives said memory access start signal to fetch dotdata from said first dynamic RAM and starts a memory access to saidsecond dynamic RAM to write attribute data and the dot data therein, andsaid display controller outputs display data of said second dynamic RAMto the exterior.
 3. A semiconductor integrated device according to claim1, wherein said second dynamic RAM is written with the drawing addressand the dot data from said dot operating section and outputs the drawnimage information to the exterior through said display controller.